AMD’s Zen 6 EPYC Venice: A Deep Dive into Performance and Architecture
AMD has unveiled its latest data center offering, the EPYC ‘Venice’ CPUs, which debut the new Zen 6 architecture. These processors represent a significant leap from the previous Zen 5, showcasing enhanced performance, architectural improvements, and expanded capabilities.
Performance and Microarchitecture
EPYC Venice is the first to feature TSMC’s N2P node, marking a 5% performance improvement over N3E. This node is not just a marginal optimization; it also brings a 18% speed improvement at the same power level and a 36% reduction in power at the same speed compared to N3E. The 256-core EPYC 9996, for instance, delivers 1,024 threads in a 2P configuration, outperforming the 768-thread 2P EPYC 9965 by 93% in SPEC CPU 2026 intrate throughput tests.
Across the board, the new architecture demonstrates a 27% average improvement in instruction per cycle (IPC) in enterprise, cloud, and AI workloads. This is particularly notable for the Zen 6c, which scales up to 32 cores, each with 4 MB of L3 cache, resulting in a total of 128 MB of L3 cache per CCD. This doubling of L3 cache per core and the doubling of cores themselves contribute significantly to the overall performance uplift.
Architectural Enhancements
The vector execution engine in Zen 6 is enhanced to support half precision AVX-512 FP16 instructions, which were not available in Zen 5. Additionally, the engine now supports either two 512-bit or four 256-bit loads, expanding the flexibility and efficiency of vector operations. The integer schedulers have also been split, with 96 shared ALU/AGU and 48 dedicated ALU entries, compared to an 88/56 split in Zen 5.
In terms of caching, the L1 data cache remains at 48 KB, while the L2 cache is increased to 1 MB. The shared L3 cache has been doubled to 48 MB, accommodating the new 12-core limit. The maximum frequency of a standard Zen 6 CCD has increased from 5 GHz to 5.3 GHz, while Zen 6c has a maximum frequency of 4.1 GHz.
Chip Topology and I/O
Venice features a dual I/O die design, with two IODs situated in the middle of the chip, flanked by Zen 6 CCDs. This topology allows for 16 memory channels per socket, supporting up to 12,800 MT/s using MRDIMMs in a 1DPC configuration. With RDIMMs, the platform supports up to 8,000 MT/s. Each 1P SP7 configuration has access to 96 PCIe 6.0 lanes, while a 2P platform has up to 128 lanes. Bonus PCIe 4.0 lanes are also available, providing flexibility in lane allocation.
For the SP8 socket, memory channels are traded for PCIe lanes, with eight channels per socket and support for up to 64 PCIe 6.0 lanes. Both platforms support CXL 3.1, ensuring compatibility with emerging data center technologies.
Quality of Life Features
AMD has introduced several quality of life features to simplify deployment and management. Unified Power Provisioning (UPP) and Utilization Based Power Scaling (UBPS) are designed to optimize power consumption based on workload needs. UPP allocates platform power across components dynamically, reducing provisioned power by 15% while increasing server density per rack. UBPS aligns power scaling with running workloads, further closing the gap between provisioned and consumed power.
The Frequency Adaptive Spectrum Technology (FAST) is particularly intriguing. It allows for two performance tiers within a single socket, enabling 32 cores to run in a “premium” category with a base clock of 3.65 GHz and a max clock of 5 GHz, while the remaining 64 cores can operate in a “batch” mode at 2 GHz with a 2.4 GHz max. This feature enhances flexibility in workload management and resource allocation.
Verano Range
AMD’s upcoming Verano range, built on the Zen 6 microarchitecture, will leverage LPDDR5X for a more flexible platform. Verano will use replaceable SOCAMM2 DIMMs, offering enhanced memory support and flexibility in deployment scenarios.
Conclusion
The EPYC Venice series represents a major step forward in AMD’s data center offerings, with significant performance improvements, enhanced architectural features, and flexible deployment options. These new processors are poised to meet the demanding requirements of modern data centers, delivering both power and performance in a more efficient and scalable manner.
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